1. Field
The present invention relates to analog-to-digital conversion.
2. Description of the Related Art
Many devices produce an analog signal that must then be converted to a digital signal for digital processing. For example, many sensors generate an analog signal that must be converted to digital before being handled by a computer.
As another example, a CMOS image circuit includes an array of pixels that output analog signals. These analog signals are then converted to digital. Many CMOS image sensors use a ramp analog-to-digital converter (ADC), which is essentially a comparator and appropriate control logic. In the conventional ramp ADC, an input voltage of the signal to be converted is compared with a gradually increasing reference voltage. The gradually increasing reference voltage is generated by a digital-to-analog converter (“DAC”) as it sequences through and converts digital codes into analog voltages. This gradually increasing reference voltage is known as the ramp voltage. In operation, when the ramp voltage reaches the value of the input voltage, the comparator generates a signal that latches the digital code of the DAC. The latched digital code is used as the output of the ADC.
The problem with the ramp ADC is that it must step through, one value at a time, all possible digital values that could be generated and output by the ADC. For example, if the CMOS sensor has a 12-bit resolution, then a 12-bit ramp ADC must be used to obtain the correct digital output. For a 12-bit ramp ADC there may be 4,096 steps in any single conversion cycle to ensure that the input voltage is converted to the appropriate digital code (one of 4,096 possibilities). This is a very long conversion period, which increases by a factor of two for every additional bit of resolution in the sensor. Since it is desirable to increase the resolution of CMOS image sensors, it is desirable to decrease the number of steps in the analog-to-digital conversion cycle.
Accordingly, a dual ramp ADC has been devised wherein a fine ADC step follows a course ADC step. During the course ADC step, the ramp voltage has a steep slope, and obtains an approximate digital value for the analog signal. For example, the more significant bits are determined. During the fine ADC step, the ramp voltage has a much more gradual slope to permit fine acquisition of the digital representation of the analog signal. Namely, the lower significant bits are determined. Unfortunately, the ramp signals during the course and fine ADC steps are not delivered to the comparator in the same manner. Namely, undesired influences like parasitic capacitance may affect the slope of the ramp signal during the course ADC step and the fine ADC differently. Stated another way, the delivery ratio of the ramp signal during the course ADC step differs from the delivery ratio of the ramp signal during the fine ADC step such that ramp signal is scaled differently during these two steps. As result, the desired changes in the ramp signal during the course and fine ADC steps are not met, and less accurate digital signals may be generated.